1. Field of the Invention
This invention relates to the technique for increasing the processing speed of an image processing apparatus.
2. Description of the Related Art
Jpn. Pat. Appln. KOKAI Publication No. 2005-78608 has disclosed the technique for alleviating the load on the CPU acting as a control block that controls an image processing apparatus capable of processing image data in blocks. In Jpn. Pat. Appln. KOKAI Publication No. 2005-78608, a sequencer block capable of accessing a processing block without the intervention of a bus is used as a control block differing from the CPU. The sequencer block controls the processing of image data which was performed in blocks by the CPU.
A protocol for data transfer used in a conventional image processing apparatus as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2005-78608 will be explained. As an example, a protocol used when the CPU writes data to the register of a processing block will be explained.
The CPU issues not only a register address, a signal representing the address of the register of a processing block to be accessed, but also a chip select signal for selecting a processing block where the register is to be written to, a register write signal for requesting register write, and a write data signal representing data to be written. When having received a chip select signal and a register write signal from the CPU, the processing block recognizes that the CPU is to perform register write, generates a write pulse, and writes the write data signal as setting data to the register according to the write pulse. The setting data is a different signal from the write pulse. The setting data of each of the CPU and sequencer is input to the processing block. The setting data to be actually written to the register of the processing block is determined, depending on which write pulse is used. After the register has been written to, the processing block generates a write completion pulse and issues a completion notice signal to the CPU in synchronization with the write completion pulse. In response the issue of the completion notice signal, the CPU recognizes the completion of the register write. As a result, a series of processes related to register write is completed.
The series of processes is an example of register write according to a protocol called a handshake protocol. In the case of register write according to such a handshake protocol, the CPU cannot perform next register write during a period from when it issues a register signal until it receives a completion notice signal. Accordingly, a register access period viewed from the CPU is a period from when the CPU issues a chip select signal until it receives a completion notice signal.
In addition to the handshake protocol, there is a fixed weight protocol which needs the issue of a specific number of cycles of chip select signals and register write signals. In this case, too, the CPU cannot perform next register write during a certain period of time.
The above example is based on the assumption that the CPU and processing block both belong to the same clock domain (or both have the same clock frequency). In the recent image processing apparatuses, the CPU and processing block both hardly belong to the same clock domain. In such a case, a process called clock transfer must be carried out during the series of processes to synchronize the CPU and processing block with each other. To realize such clock transfer, a process according to a handshake protocol has to be carried out.
A protocol for data transfer when clock transfer is needed will be explained with reference to FIG. 5. As described above, the CPU issues not only a register address ADD but also a chip select signal CS_X, a register write signal WE_X, and a write data signal (not shown). These signals are all in synchronization with operation clock CL_CPU of the CPU.
Having received the chip select signal CS_X and register write signal WE_X from the CPU, the processing block generates a write pulse cpu_wgin synchronizing with the operation clock CLK_CPU of the CPU. The processing block generates a write pulse wgin synchronizing with operation clock CLK_BLK of the processing block from the write pulse cpu_wgin and writes write data to the register according to the write pulse wgin. After the register write has been completed, the processing block generates a write completion pulse wg_valid synchronizing with the operation clock CLK_BLK and further generates a write completion pulse cpu_valid synchronizing with the operation clock CLK_CPU of the CPU from the write completion pulse cpu_valid. Then, the processing block issues a completion notice signal WAIT in synchronization with the write completion pulse cpu_valid. As a result, the CPU completes the register write. With such a series of processes, even when the clock domain of the CPU differs from that of the processing block, register write can be performed, while the CPU and processing block are synchronizing with each other properly.
During the series of processes, too, the CPU cannot perform next register write during the period from when it issues a register write signal until it receives a completion notice signal. Accordingly, even in the case of FIG. 5, the register access period viewed from the CPU is the period from when the CPU issues a chip select signal CS_X until it receives a completion notice signal WAIT.